Programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs) or complex programmable logic devices (CPLDs), may be programmed with configuration data to provide various user-defined features. In certain applications, configuration data may be programmed into an external non-volatile memory such as a flash memory. The configuration data may be loaded from the external non-volatile memory into the PLD and programmed into volatile configuration memory of the PLD upon power-up, in response to an appropriate instruction, or in response to the toggling of an appropriate pin of the PLD. When a user desires to change the behavior of the PLD, the external non-volatile memory may be erased and reprogrammed with new configuration data that is subsequently loaded into the PLD.
Unfortunately, the above approach presents several potential problems for reliable PLD operation. Specifically, if the configuration data stored in the external non-volatile memory becomes corrupted or an erroneous configuration data pattern is loaded into the external non-volatile memory, then the operation of the PLD may become inoperable or exhibit unpredictable behavior after the PLD is programmed with the configuration data pattern. Similarly, if an otherwise valid configuration data pattern is improperly programmed or reprogrammed into the PLD or the external non-volatile memory as a result of, for example, a power failure, then the operation of the PLD may be likewise affected. Accordingly, there is a need for an improved approach to the loading of PLD configuration data that, for example, reduces the likelihood of erroneous configuration data being loaded into configuration memory of the PLD.